1. Technical Field
The present invention relates to a method and apparatus for data processing in general, and in particular to a method and apparatus for floating-point processing within a computer system. Still more particularly, the present invention relates to a method and apparatus for generating an end-around carry for an end-around carry adder in a floating-point pipeline within a computer system.
2. Description of the Prior Art
Within a computer system, a floating-point pipeline typically operates in a sign-magnitude format; that is, the sign and magnitude of an operand within the floating-point pipeline are represented by separate bits as specified in the IEEE-754 floating-point standard. According to the IEEE-754 floating-point standard, a floating-point number w, for example, is represented by three components, namely, a sign, an exponent, and a mantissa. The most significant bit of the floating-point number w is the sign bit. The next eight bits are the exponent. The exponent is represented in an "excess -127" format in which a "bias" of 127 is added to the actual exponent to yield the 8-bit exponent. The mantissa is represented by a 23-bit fraction preceded by an implied "1" for a normalized number or without the implied "1" for an un-normalized number.
Typically, addition and subtraction of two floating-point operands are performed by a sign-magnitude adder embedded within one of the stages of the floating-point pipeline. In order to perform a subtraction (or more appropriately, an addition of a negative operand), one of the two operands must be inverted internally within the sign-magnitude adder. According to the one's complement representation, an end-around carry is required to complete such an inversion. Generally speaking, methods for end-around carry generation are well-known; however, the processing speed of these prior art methods are satisfactory at best. The delays in cycle time within the floating-point pipeline attributed to the prior art methods for end-around carry generation are significantly worse when wider adders, such as those utilized to perform double-precision arithmetic, are utilized. Consequently, it would be desirable to provide an improved method for generating an end-around carry in a floating-point pipeline within a computer system.